1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and, more particularly, to a semiconductor device including a semiconductor element formed on an insulating layer and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, a three-dimensional integrated circuit including active elements layered in a three-dimensional manner is known as aiming to enhance integration density and functions of a semiconductor device. In a specific configuration, semiconductor layers and insulating layers are alternately layered. Then, active elements are formed in respective semiconductor layers. Such a structure including semiconductor layers (Si thin films) formed on insulating layers is referred to as a SOI (Silicon On Insulator) structure.
FIG. 14 is a sectional view illustrating a semiconductor device of a conventional SOI structure. Referring to FIG. 14, the semiconductor device of a SOI structure comprises a semiconductor substrate 101, a p well 102 formed in a prescribed region of the surface of semiconductor substrate 101, a n well 103 formed adjacent to p well 102, n-type impurity regions 104, 105 formed in p well 102 with a prescribed space between them, a gate electrode 108 formed on p well 102 between n-type impurity regions 104 and 105 with an insulating film interposed, p-type impurity regions 106, 107 formed in n well 103 with a prescribed space between them, a gate electrode 109 formed on n well 103 between p-type impurity regions 106, 107 with an insulating film interposed, an insulating layer 21 formed to cover the whole surface, and a wiring layer 110 formed in a contact hole 21a provided in insulating layer 21 to be electrically connected to gate electrode 109. In such a configuration, a semiconductor element (a CMOS) of a first layer is formed beneath insulating layer 21.
The semiconductor device further comprises a SOI film (a semiconductor film) 22 formed with a prescribed width on insulating layer 21, a gate oxide film 23 formed to cover SOI film 22, a gate electrode 24 formed on gate oxide film 23 and insulating layer 21, and an oxide film 25 formed on gate electrode 24 and on wiring layer 110. A channel region 22c is formed in the upper part of SOI film 22. A semiconductor element (a MOS transistor) of a second layer is formed with SOI film 22, gate oxide film 23, and gate electrode 24.
FIG. 15 is an enlarged plan view of the SOI structure portion of the semiconductor device illustrated in FIG. 14. FIG. 16 is a sectional view of the semiconductor device illustrated in FIG. 15 taken along the line X--X. Referring to FIGS. 15 and 16, the conventional SOI structure will be described. n-type impurity regions 22a, 22b are formed in SOI film 22 on insulating layer 21 in a direction crossing gate electrode 24 with a prescribed space between them. Impurity regions 22a, 22b are formed in a region including the upper edge portion of SOI film 22. Specifically, impurity regions 22a, 22b are formed to reach a prescribed depth from the upper surface toward the bottom surface of SOI film 22. Then, a source contact 26 is formed on impurity region 22a. A drain contact 28 is formed in impurity region 22b. A gate contact 27 is formed in a prescribed position in gate electrode 24.
FIG. 17 is a cross sectional view for describing a process for manufacturing the semiconductor device illustrated in FIG. 16. Referring to FIG. 17, the process for manufacturing the semiconductor device will be described in the following.
First, as illustrated in FIG. 17(a), a SOI film 22 comprising a mono-crystal silicon film having a thickness of approximately 5000 .ANG. is formed on insulating layer 21.
Next, as illustrated in FIG. 17(b), patterning is performed on SOI film 22 by performing anisotropic etching. Then, the upper side ends of SOI film 22 patterned by anisotropic etching are of angular shapes of approximately 90.degree..
Next, as illustrated in FIG. 17(c), a gate oxide film 23 is formed over SOI film 22.
Next, as illustrated in FIG. 17(d), a gate electrode 24 comprising polysilicon is formed to cover gate oxide film 23.
Next, as illustrated in FIG. 17(e), a n-type impurity region (not shown) is formed by ion implantation of an impurity using gate electrode 24 as a mask. A channel region 22c is formed by this. Then, an oxide film 25 is formed to cover gate electrode 24.
Conventionally, a semiconductor device of SOI structure was formed as described above.
As described above, in a semiconductor device of a conventional SOI structure, SOI film 22 was patterned by performing anisotropic etching on SOI film 22.
According to the process of anisotropic etching performed on SOI film 22, however, the upper side ends of SOI film 22 are of angular shapes, and then there was a problem that in the case of the angular shapes being acute angles of less than 90.degree., a dielectric breakdown tends to be caused by electric field concentration. In a SOI structure illustrated in FIG. 9, a channel region is formed also on the upper side ends of SOI film 22. Therefore, there was a problem that if the upper side ends of SOI film 22 are of angular shapes, it adversely affects the control characteristics of a transistor.
Conventionally, various methods have been proposed as a method of rounding off the angular shapes of the upper side ends of SOI film 22. These are disclosed in, for example, Japanese Patent Laying-Open No. 60-163457 (1985). FIG. 18 is a sectional view illustrating a semiconductor device of the disclosed SOI structure. FIG. 19 is a partial enlarged view of a part A of the semiconductor device illustrated in FIG. 18. Referring to FIGS. 18 and 19, according to the proposed technique, an element forming region (a SOI film) 32 is formed on an insulating layer 31. Then, an insulating film 33 is formed on element formation region 32. The angular shapes of the upper side ends of element formation region 32 are rounded off by isotropic etching using insulating film 33 as a mask. If one of the shapes rounded off by isotropic etching is enlarged, it is a shape as illustrated in FIG. 19. Specifically, the shape as a whole is a rounded shape, while, to be precise, two angular parts 32a, 32b in which each of straight lines tangent to the etched curve at respective parts 32a, 32b makes an angle of 90.degree. with a surface of element formation region 32 are newly formed. There is a possibility that angular parts 32a, 32b cause a dielectric breakdown due to electric field concentration. Therefore, according to the proposed conventional technique, it is considered difficult to effectively prevent the dielectric breakdown caused by electric field concentration.
Another proposed example is disclosed, for example, in Patent Laying-Open No. 1-295463 (1989). FIG. 20 is a plan view illustrating a semiconductor device of the proposed SOI structure. FIG. 21 is a sectional view of the semiconductor device illustrated in FIG. 20 taken along the line X--X. Referring to FIGS. 20 and 21, the proposed semiconductor device comprises a Si monocrystal plate (a semiconductor substrate) 40, a field insulating film (an insulating layer) 41 formed over Si monocrystal plate 40, a semiconductor island (a SOI film) 42 formed on field insulating film 41, dummy insulating films 45 formed on the sidewall parts of semiconductor island 42, a gate insulating film 43 formed over semiconductor island 42 and dummy insulating films 45, and a gate electrode 44 formed on gate insulating film 43. According to the proposed technique, a method is employed in which dry oxidation is performed at about 1200.degree. C. for approximately 6 hours for the purpose of rounding off the upper side ends of semiconductor island (SOI film) 42.
However, normally, in a semiconductor device of a SOI structure, a semiconductor device is formed beneath field insulating film (an insulating layer) 41. Then, there is a problem that if thermal oxidation is performed on such a semiconductor device at 1200.degree. C. for 6 hours, characteristics of the semiconductor element of the lower layer are changed. Therefore, it is considered difficult to apply the proposed method to a semiconductor device of a SOI structure in which an element such as a CMOS is formed in a lower layer. Furthermore, in the proposed example, dummy insulating films 45 are formed on both sidewall parts of semiconductor island 42, and a channel region 42c is formed only in the upper central part of semiconductor island 42. The upper side ends of semiconductor island 42 do not influence the characteristics of the transistor themselves. An example is considered in which the proposed improved example is applied to the semiconductor device illustrated in FIG. 16, for example. FIG. 22 is a sectional view illustrating an example in which the conventional proposed example illustrated in FIG. 21 is applied to the conventional semiconductor device illustrated in FIG. 16. Referring to FIG. 22, if the proposed example is applied to the conventional semiconductor device illustrated in FIG. 16, a channel region of a semiconductor island 52 is formed also on the sidewall parts of semiconductor island 52. Therefore, dummy insulating films 45 formed on the sidewall parts of semiconductor island 52 function as gate insulating films. Specifically, part of the gate insulting film on the channel region 52c has a thickness different from that of the other part. Consideration is given to a resulting drawback that it adversely affects the control characteristics of the transistor, and the characteristics of the transistor cannot be enhanced.
As described above, conventionally, it was difficult to effectively prevent a dielectric breakdown without adversely affecting the characteristics of the transistor. It was also difficult to round off the upper side ends of the semiconductor layer without adversely affecting the semiconductor element formed in the lower layer.